SAN JOSE, Calif. -- Sidense Inc. has rolled out a line of one-time programmable (OTP) memory macrocells for use in low-power and cost-sensitive applications.
The IP, dubbed Sidense Low Power (SLP), are aimed for storage, implantable medical devices, RFID, handheld wireless communication devices, analog trimming, and power and energy management.
Based on Sidense's split-channel architecture, SLP memory macrocells are said to be small. A 256-Kbit memory takes less than 0.5-mm2 of silicon.
Power dissipation claims to be low. Typical read current for a 256 Kbit macro is 0.25uA/MHz/bit with a 2.5V read voltage. Based on a 180-nm process, SLP macros are available in densities up to 256 kbits and multiple blocks may be stitched together for larger memory capacity.
''While SLP technology is one-time programmable, macros may be used in an emulated multi-time programmable (eMTP) mode through the use of uncommitted memory segments that can later be programmed in the field to update code, security key or other data storage,'' according to the Ottawa, Canada-based IP firm.
''SLP macros feature two additional read modes with enhanced margins and data security for highly reliable, field-programmable systems -- differential and redundant read modes,'' according to the company.
The IP requires no additional masks or process steps, thus adding no extra wafer processing cost, according to the company.
